The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and low capacitance (e.g., low dielectric constant) interconnect properties.
In particular, in forming multi-level wiring in forming a semiconductor device, the formation of wiring interconnects requires several different steps including etching, ashing and wet cleaning. For example in the formation a dual damascene at least two separate etching and ashing steps are required. For example, silicon oxide based low-K dielectric insulating layers have exhibited a tendency to interact with oxygen containing plasmas in the ashing and dry etching steps to contaminate and detrimentally affect the low-K dielectric insulating layers.
Subsequent processes in the prior art including separate wet cleaning steps to remove contaminants such as fluorine from the surface and baking steps to remove adsorbed water from the low-K dielectric insulating layer have been required to improve degraded dielectric constants caused by plasma processes. In addition, other etching species can react with the low-K dielectric insulating layer contaminating it as well as making it more susceptible to moisture absorption during subsequent processing steps.
Approaches in the prior art to overcome moisture absorption and contamination of low-K silicon oxide based dielectric insulating layers have included wet cleaning processes followed by time-consuming baking processes to drive the absorbed moisture out of the low-K dielectric insulating layer. However, baking the dielectric insulating layer does not repair plasma processing damage such as the formation of dangling or coordinatively unsaturated silicon bonds or silanol bonds formed by interaction of the dielectric insulating layer with plasma species. Plasma treatments to repair plasma damage have met with limited success due to the tendency to form additional plasma damage to the dielectric insulating layer, as well as any repair being limited to very near surface regions.
There is therefore a need in the semiconductor processing art to develop a silicon oxide based low-K dielectric insulating layer treatment to repair plasma processing damage.
It is therefore an object of the invention to provide a silicon oxide based low-K dielectric insulating layer treatment to repair plasma processing damage, in addition to overcoming other shortcomings and deficiencies in the prior art.